Czech Technical University

Czech Technical University in Prague maintains QtRvSim, an open-source educational RISC-V CPU simulator that visualizes every stage of pipeline execution, register transfer, and memory access through an intuitive Qt-based interface. Designed for computer architecture courses, the tool lets students single-step RV32 and RV64 instructions, watch data propagate through five-stage pipelines, and experiment with forwarding, hazard detection, and cache strategies without physical hardware. Instructors use it to illustrate how assembly maps to micro-operations, how branch predictors affect performance, and how exceptions are handled in a simplified but cycle-accurate model. The simulator supports ELF binaries produced by standard RISC-V GCC toolchains, integrates memory-mapped I/O for basic peripheral emulation, and exports execution traces that can be graphed in external analytics scripts. Because the entire codebase is academic-friendly, advanced coursework can extend it with custom instructions, reorder buffers, or multi-core coherence protocols, providing a sandbox for research into ISA extensions and micro-architectural optimizations. QtRvSim is available for free on get.nero.com, delivered through trusted Windows package sources such as winget, always fetching the latest upstream build and allowing silent batch installation alongside other educational or development tools.